1. Field of the Invention
The present invention relates to a semiconductor device capable of performing high speed writing and reading operation, and particularly relates to a construction of a semiconductor memory device in which page mode operation and nibble mode operation can be selected according to an external mode designation signal.
2. Description of the Prior Art
As one of the methods for reading and writing data in a dynamic type semiconductor memory device, an operation mode called "page mode" is known. The page mode is disclosed for example in U.S. Pat. No. 4,156,938 to R. J. Proebsting et al., MOSTEK Corp., entitled "MOSFET MEMORY CHIP WITH SINGLE DECODER AND BI-LEVEL INTERCONNECT LINES", filed Dec. 29, 1975.
FIG. 7 is a timing chart in the page mode, showing external control signals applied to a dynamic type semiconductor memory device and the read out data. Referring to FIG. 7, data reading operation in the page mode will be described in the following.
Such a semiconductor memory device receives row addresses and column addresses sequentially and therefore, in order to latch these addresses, strobe signals called RAS (row address strobe) and CAS (column address strobe) are applied respectively to the semiconductor memory device.
First, an external row address strobe signal provided from the exterior (hereinafter referred to as Ext. RAS) goes into an active state at a logical level "L" (hereinafter referred to simply as "L") to enable the semiconductor memory device. The signal Ext. RAS is applied to an RAS buffer circuit. With the change of Ext. RAS to "L" serving as a trigger, an internal RAS signal (hereinafter referred to as Int. RAS) goes to "H" and is applied to an address buffer circuit from the RAS buffer circuit. With the change of the Int. RAS to "H" serving as a trigger, the address buffer circuit accepts a row address and then produces an internal row address. The internal row address is applied to a row decoder, where a single word line (row) corresponding to the row address is selected.
Subsequently, an external column address strobe signal (hereinafter referred to as Ext. CAS) is brought into an active state at "L" and is applied to an internal CAS buffer circuit. An internal CAS signal (hereinafter referred to as Int. CAS) changing from "L" to "H" with the change of Ext. CAS as a trigger is applied from the internal CAS buffer circuit to the address buffer circuit. With the change of Int. CAS to "H" serving as a trigger, the address buffer circuit accepts a column address and produces an internal column address. The internal column address is applied to a column decoder, where one bit line (column) corresponding to the column address is selected. By the above described operation, one memory cell specified by the row address and the column address is selected and the data stored in this selected memory cell is read out.
Then, Ext. CAS is brought into an inactive state at "H" and an internal CAS signal (hereinafter referred to as Int. CAS) outputted from the internal CAS buffer circuit changes from "L" to "H". By this Int. CAS at "H", the column decoder and the data output circuit are reset. Subsequently, Ext. CAS goes again to "L" and a new column address is accepted. A bit line corresponding to this new column address is selected and the data in a newly selected memory cell is read out. The above described operation is repeated during a period of "L" of Ext. RAS. Consequently, it can be understood that the page mode is a mode in which bit lines are selected by changing only column addresses and data are successively read out of the memory cells connected to one word line since the row address is held in the same state. By this sequential operation, it is made possible to read data at high speed since it is not necessary to designate all the rows and columns. Writing of data can be made by using an input buffer circuit instead of the output buffer circuit, causing data to flow in the opposite direction.
Contrary to the above, new method for reading and writing data called "nibble mode" has been proposed recently and this nibble mode tends to be practically applied in such devices as a 64K bit dynamic RAM, 256K dynamic RAM etc. The nibble mode is disclosed for example in "A 100 ns 64K Dynamic RAM using Redundancy Techniques" by S. S. Eaton, S. S. Shefield et al., Inmos Cop., ISSCC Dig. of Technical Papers, page 84-page 85, February, 1981 or in U.S. Pat. No. 4,344,156 to S. S. Eaton Jr., D. R. Wooten, Inmos Corp., entitled "High Speed Data Transfer for a Semiconductor Memory", filed Oct. 10, 1980.
FIG. 8 shows an example of a construction of a 64K bit dynamic RAM in which nibble mode operation can be effected. Referring to FIG. 8, the construction of the RAM will be described specifically in connection with a memory portion, a word line selecting system, a bit line selecting system and a data output system.
The memory portion includes 256 word lines WL0 to WL255 and 256 bit lines BL0 to BL255. Corresponding to each point of intersection between a word line and a bit line, one memory cell MC is provided, the respective memory cells being connected with the associated word lines and bit lines. The memory portion is divided into two sections each including 32K bits. At the center of the memory portion, sense amplifiers SA0 to SA255 for amplifying data bits are connected to the bit lines BL0 to BL255, respectively.
The word line selecting system comprises: an RAS buffer circuit RB for applying the Int. RAS to each of the address buffer circuits A0 to A7 upon receipt of the signal Ext. RAS; address buffer circuits A0 to A7 for receiving a row address in response to the Int. RAS so as to apply a row address signal to a row decoder; and the row decoder RD for decoding the row address signal from the address buffer circuits A0 to A7 so as to select a word line corresponding to the row address signal.
The bit line selecting system comprises: a CAS buffer circuit CB for applying the Int. CAS to the address buffer circuits A0 to A7 upon receipt of the signal Ext. CAS; address buffer circuits A0 to A5 for receiving a column address upon receipt of the Int. CAS so as to apply a column address signal to a column decoder CD; and the column decoder CD for decoding the column address signal received from the address buffer circuits A0 to A5 so as to select simultaneously four bit lines.
The data output system comprises: data registers DR1 to DR4 for holding the four bit data, each by one bit, selected by the column decoder CD through the corresponding sense amplifiers, column decoder CD and signal lines I/O1 to I/O4; and an output buffer circuit OB for serially applying the signals received from the data registers to an external apparatus. In the paths connecting the data registers DR1 to DR4 with the output buffer circuit OB, switches SW1 to SW4 each comprised of a field-effect transistor are provided respectively. The gate electrodes of the transistor switches SW1 to SW4 are connected respectively via signal lines Y.sub.1N to Y.sub.4N to data selectors DS1 to DS4 which control the states of the switches SW1 to SW4 respectively. The data selectors DS1 to DS4 form a shift register SR. To the shift register SR constructed by the data selectors DS1 to DS4, the signals from the address buffer circuits A6 and A7 are applied so that the data corresponding to the signals are selected. As a result, the switches corresponding thereto are selected to be turned on so that the data stored in the corresponding data registers are read out. The signal Int. CAS from the CAS buffer circuit CB is also applied to the data registers DR1 to DR4, the shift register SR and the output buffer circuit OB so as to control the operation timing of the respective circuits.
FIG. 9 is an operation timing chart concerning external control signals and data read out in the nibble mode in a semiconductor memory device of FIG. 8. In the following, the nibble mode operation will be described with referring to FIGS. 8 and 9.
First, the signal Ext. ovs/RAS/ goes to "L" so that the RAS buffer circuit RB is enabled. With the change of Ext. RAS to "L" serving as a trigger, the Int. RAS outputted from the RAS buffer circuit RB changes from "L" to "H". With the change of Int. RAS from "L" to "H" serving as a trigger for the address buffer circuits A0 to A7, the row address signal is accepted in the address buffer circuits A0 to A7 and the row decoder RD so that a word line corresponding thereto is selected among the 256 word lines WL0 to WL255.
Subsequently, the signal Ext. CAS goes to "L" and this change to "L" serves as a trigger to enable the CAS buffer circuit CB. As a result, the Int. CAS outputted therefrom changes from "L" to "H". In synchronism with Int. CAS to "H", the address buffer circuits A0 to A7 are activated to receive the column address signal. The output signals from the address buffer circuits A0 to A5 are applied to the column decoder CD so that the column decoder CD selects simultaneously along the 256 bit lines BL0 to BL255, four successive bit lines corresponding to the column address signals from the buffer circuits A0 to A5. By the above described operation, four memory cells are selected and the data in the selected memory cells are applied to the data registers DR1 to DR4 via the sense amplifiers, the column decoder CD and the signal lines I/O1 to I/O4. The data registers DR1 to DR4 hold respectively the data applied thereto. At this time, Int. CAS is also applied to the shift register SR and the output buffer circuit OB, which are in the enabled state. The signals from the address buffer circuits A6 and A7 is applied to the shift register SR so that data selectors corresponding thereto are selected and the corresponding transistor switches are in ON state. As a result, the data stored in the data registers connected to the conducted switches are provided through the output buffer circuit OB.
Then, as shown in FIG. 9, in the state of Ext. RAS at "L", the signal Ext. CAS is first brought into "H" and then brought again to "L". In consequence, the shift register SR operates so that the first selected and conducted switch is brought into the non conductive state and a succeeding switch is conducted. For example, if only the switch SW1 is first selected and conducted by the data selector DS1 in response to the signal from the address buffer circuits A6 and A7, the switch SW1 is then brought into the non conductive state and only the switch SW2 is conducted. By repeating this operation, the shift register SR operates independent of an external address, and the first selected four-bit data are successively read out.
Thus, in the nibble mode, Ext. CAS changes in the sequence of "H".fwdarw."L".fwdarw."H".fwdarw."L" with Ext. RAS being held at "L", whereby the data stored in the data registers DR1 to DR4 are successively read out. Writing of data can be made by using an input buffer circuit instead of the output buffer circuit, causing data to flow in the opposite direction.
As described above, in the nibble mode, differing from the page mode, there is no need to designate a column address each time for selection of a bit line and data can be read out at higher speed than in the page mode. However, the nibble mode has a disadvantage that only the first selected four-bit data can be read out.
Thus, although operation in a semiconductor memory device in the page mode is substantially different from that in the page mode as described above, the timing of Ext. RAS and that of Ext. CAS are entirely the same in the two modes as can be seen from FIGS. 7 and 9, and therefore, it is possible to support only either of the two modes in a conventional semiconductor memory device since it cannot identify its operating mode.